Multi-Core Processor (MCP) technology has traditionally been applied to a system to perform a specific function in an application. The characteristics of each core's technology are different, and, therefore, such an approach does not work well when two or more cores are mixed. The design inflexibility forces continuous use of one technology. For an example, in a symmetric MCP, there can be a Main Processing Element (MPE) and Synergetic Processor Elements (SPE). In addition, each hybrid design requires customized integration of different component technologies. This is time-consuming, and is subject to design error and mistakes. Moreover, ever-increasing interconnect complexity prevents design scalability. Still yet, different technology components present compatibility and efficiency problems. Previous core collaboration is limited to conventional direct-computation mode without much flexibility. Such an approach reduces overall performance gain available from the integration. Moreover, conventional data bus requires custom design per system. This requirement is time consuming, prone to error, and inefficient.
U.S. Pat. No. 7,624,250 discloses a multi-core processor. The cores have different functional operability and include a chain of multiple unidirectional connections spanning processor cores, terminating in registers within the respective processor cores.
U.S. Pat. No. 7,209,996 discloses a multi-core and multi-threaded processor that includes four threaded cores and/or a crossbar that incorporates the cache memory.
U.S. Patent Application 20060136605 discloses multi-core multi-thread processor crossbar architecture. The crossbar includes an arbiter functionality to sort multiple requests.
U.S. Pat. No. 7,676,669 discloses a processor control method. Yield improvements are claimed to be attained with the aid of partial core quality product chips that are activated by a core selection flag register that maintains the status us each core and controls the output to the core block from the processor common block.
U.S. Pat. No. 7,047,340 discloses a data bus method for the communication between two assemblies.
U.S. Patent Application 20100088453 discloses an architecture and method. Embodiments provide alternatives to the use of external bridge IC architecture by using a multiplex of peripheral bus so that multiple processors can use one peripheral interface slot without requiring an external bridge.